In modern communication systems, data are typically transmitted serially. These data are clocked, i.e., sent synchronously with a clock signal, which is normally not transmitted. For a receiver to recover the incoming signal accurately, it is crucial that the receiving end be able to extract a clock frequency from the incoming data signal and then use the recovered clock frequency to decipher the received signal. Phase lock loops (PLL) have been used extensively for such clock data recovery (CDR). A CDR circuit typically consists of three main components: a phase detector, a loop filter, and a phase generator. FIG. 1 shows the configuration of a typical CDR circuit. The phase detector 52 compares an incoming data signal 50 with a sampling clock signal 62 generated by the phase generator 58 to determine if the signals 50, 62 are in phase. If the data signal 50 and the sampling clock signal 62 are not in phase, then an error signal is sent to the loop filter 54, which eliminates unwanted high frequency noise. The phase generator 58 takes inputs from the loop filter 54 and a timing reference signal 56 to adjust the signal 62 at output 60 in an effort to minimize the phase error between the output signal 62 and the incoming data 50.
However, for high speed serial communication in the gigabit per second range, CMOS processing technology is being pushed to its limit and manufacturing yields are low while, on the other hand, alternative technologies are costly.
An alternative technique to circumvent this dilemma calls for a divider unit at the receiving end to turn the serial data stream into two parallel data streams, effectively reducing the required processing speed of the phase detector by half. An example of this technique is taught by Anderson in U.S. Pat. No. 5,953,386. To achieve further clock speed reduction, additional dividers are required to be placed downstream of the first divider.
It would be desirable to have a simpler and more flexible clock data recovery technique that can recover data from a high speed serial transmission using a substantially reduced clock speed without the need for multiple stages of dividers.
With regard to the phase detector 52 of FIG. 1, traditionally either an XOR gate or an edge-triggered JK flip-flop has been used to extract a clock signal. FIG. 2 shows the operation of a phase detector using an XOR gate. Timing charts a1 and b1 represent the inputs into the XOR gate. Pulses 11 and 13 on charts a1 and b1 are 90 degrees out of phase with one another. The output of the XOR gate, shown in timing chart c1, has an average level of half of the peak value compare levels 12 and 22 where 12 is the average level and 22 is the maximum. For a CDR that uses an XOR gate as phase detector, this average level 12 denotes the absence of a phase error. When the phase difference between the input signals a1 and b1 deviates from 90 degrees, the average level changes, signifying the presence of phase error. For instance, in the case when the input signal b1′ lags the input signal a1′ by more than 90 degrees, e.g. pulse 17 lags pulse 15, the average value of the output c1′, level 24, raises above the half way level 12 and the phase error 16 in c1′ becomes positive. On the other hand, when the input signal b1″ lags the input signal a1″, e.g. pulse 21 lags pulse 14, 19 by less than 90 degrees, e.g. amount 18, the XOR output c1″ would have an average difference 20 below the half-way level 12.
FIG. 3 shows the operation of a JK flip-flop as a phase detector 52. The first set of timing signals 32 shows the case when no error signal is produced. For a JK flip-flop, when the inputs J and K are 180 degrees out of phase from one another 38, the output Q would produce a function having an average level 40 that is half of the peak value 39. The second set of timing signals 34 shows the case when a positive error is produced. In this case, K′ lags J′ by more than 180 degrees 42, resulting in an output function Q′ that has an average level 44 that is higher than the half way point level 40. The third set of timing signals 36 shows the case when a negative phase error is produced. In this case, K″ lags J″ by less than 180 degrees, e.g. amount 46, and as a result, the output of the JK flip-flop 30 has any average level 48 that is less than the half way point level 40.
Although both of the above mentioned phase detection methods use digital components, the methods still have to rely on analog components to extract the phase error information. It is the object of the present invention to achieve a phase detection method that permits full digital implementation.